In the current field of semiconductor devices, methods of reducing cost merely by decreasing a characteristic size encounter bottlenecks. Particularly when the characteristic size is decreased below 150 nm, many physical parameters of semiconductor devices cannot be scaled down in proportion, for example, a Si band gap Eg, a fermi potential φF, an interfacial state and oxide layer charge QOX, a thermoelectric potential Vt, a self-built potential of a pn junction, etc. These parameters affect the performance of the device which is scaled down in proportion. If it is desired to maintain beneficial and good properties of the device, the technology of enhancing carrier mobility is significant in scaling-down the CMOS in proportion. The switching speed of the device is enhanced by increasing the carrier mobility in the strained Si technology, which becomes a hot point for current research.
In order to further improve the device, strain is introduced to a channel region of a MOSFET, by using one or more different processes, to enhance the carrier mobility. For example, on a wafer with a crystal face of (100), a crystal orientation of the channel region is <110>. In a PMOS device, a compressive stress is used in a longitudinal direction (source/drain direction), and a tensile stress is used in a horizontal direction; while in a NMOS device, a tensile stress is used in a longitudinal direction, and a compressive stress is used in a horizontal direction. Recently, in a logic device with good properties, strained silicon, obtained by a planar coaxial process, is used. It has been developed to introduce a channel strain by depositing nitride cap layers (contact etch stop layer (CESL) SiN) with different types of stresses on the device structure. For example, SiN with a tensile stress is capped in a NMOS device to induce the channel strain and thus enhance the carrier mobility of the NMOS device. Similarly, a nitride cap layer with a compressive stress may be formed on a PMOS device structure to increase the carrier mobility of the PMOS device. For a NMOS device, a tensile stress of up to about 1.4 GPa is obtained by induction with the SiN film using the above process, and for the PMOS device, a compressive stress of up to about 3.0 GPa is obtained by induction with the SiN film using the above process.